|تعداد مشاهده مقاله||9,077,024|
|تعداد دریافت فایل اصل مقاله||5,928,330|
Design a PLL for Fractional Frequency Synthesizers using DDSM with Reduced Hardware
|International Journal of Industrial Electronics Control and Optimization|
|دوره 5، شماره 2، شهریور 2022، صفحه 177-187 اصل مقاله (1.35 M)|
|نوع مقاله: Research Articles|
|شناسه دیجیتال (DOI): 10.22111/ieco.2022.41006.1402|
|Leila Jahanpanah1؛ Seyed Ali Sadatnoori 2؛ Iman Chaharmahali3|
|1Department of electrical engineering, Mahshahr branch, Islamic Azad university, Mahshahr, Iran|
|2Department of electrical engineering, Shoushtar branch, Islamic Azad university, Shoushtar, Iran|
|3Department of electrical engineering, Andimeshk branch, Islamic Azad university, Andimeshk, Iran|
|Phase locked loop (PLL) circuits are widely used in fractional frequency synthesizers. In these synthesizers, fractional multiples of the reference frequency can be synthesized, so the reference frequency and the bandwidth of the loop can be increased. This frequency synthesizer is commonly used due to its flexibility and convenient frequency adjustment. In this paper, a PLL circuit of the transistor level is designed in which a hybrid digital sigma-delta modulator with reduced hardware is used. This Digital Delta-Sigma Modulator (DDSM) has four stages that have a lower noise level and power consumption than the conventional type. This PLL circuit has a third-order loop filter and a voltage-controlled oscillator of the NMOS type. In the PLL circuit, two counters are used in its feedback path. In the proposed divider, there is a dual divider P / P + 1 (in this case 5, 6) which divides its input signal by 5, 6 according to the control input. A design example for the PLL is provided. A third stage digital Delta-Sigma modulator with reduced hardware is also used to control these counters. This modulator has less power consumption than the conventional method and has less number of transistors by 85%.|
|Digital delta-sigma modulator؛ Fractional frequency synthesizers؛ Hybrid modulators؛ Spurious tones؛ Phase locked loop|
 K. Hosseini and M.P. Kennedy, Minimizing Spurious Tones in Digital Delta–Sigma Modulators, Springer, pp. 100-150, New York, 2011.
 S. Pamarti, J. Welz and I. Galton, “Statistics of the quantization noise in 1-bit dithered single-quantizer digital delta–sigma modulators”, IEEE Trans. Circuits Syst.I, Regular Paper, Vol. 54, No. 3, pp. 492–503, 2007.
 S. Pamarti and I. Galton, “LSB dithering in MASH deltasigma D/A converters”, IEEE Trans. Circuits Syst. I, Regular Papers, Vol. 54, No. 4, pp. 779–790, 2007.
 M.P. Kennedy, H. Mo and B. Fitzgibbon, “Spurious tones in digital delta-sigma modulators resulting from pseudorandom dither”, journal of the Franklin Institute, pp. 1-20, 2015.
 M.P. Kennedy, B. Fitzgibbon and K. Dobmeier, “Spurious Tones in Digital Delta-Sigma Modulators with Pseudorandom Dither”, 978-1-4673-5762-IEEE, pp. 27472750, 2013.
 V.R. Gonzalez-Diaz, M.A. Garcia-Andrade, G.E, FloresVerdad and F. Maloberti, “Efficient dithering in MASH sigma–delta modulators for fractional frequency synthesizers”, IEEE Trans. Circuits Syst.I, Regular Papers, Vol. 57, No. 9, pp. 2394–2403, 2010.
 M. Borkowski and J. Kostamovaara, “Variable modulus deltasigma modulation in fractional-N frequency synthesis”, Electronics Letters, Vol. 43, No. 25, pp. 1399-1400, 2007.
 K. Hosseini and M.P. Kennedy, “Maximum sequence length MASH digital delta-sigma modulators”, IEEE Trans. Circuits Syst.I, Regul. Pap. Vol. 54, No. 12, pp. 2628–2638 2007.
 K. Hosseini and M.P. Kennedy, “Architectures for maximum sequence length digital delta–sigma modulators”, IEEE Trans. Circuits Syst.II, Express Briefs, Vol. 55, No. 10, pp. 1104–1108, 2008.
 K. Hosseini and M.P. Kennedy, “Mathematical analysis of a prime modulus quantizer MASH digital delta–sigma modulator”, IEEE Trans.Circuits Syst.II, Express Briefs, Vol. 54, No. 12, pp. 1105–1109, 2007.
 J. Song and I.C. Park, “Spur-free MASH delta–sigma modulation”, IEEE Trans.CircuitsSyst.I, Regular Papers, Vol. 57, No. 9, pp. 2426–2437, 2010.
 K.J. Wang, A. Swaminathan and I. Galton, “Spurious Tone Suppression Techniques Appliedto a Wide-Bandwidth 2.4 GHz Fractional-N PLL”. IEEE Journal on Solid-State Circuits, Vol. 43, No. 12, pp. 2787–2797, 2008.
 M.P. Kennedy, H. Mo, B. Fitzgibbon, A. Harney, H. Shanan and M. Keaveney,“ 0.3–4.3 GHz Frequency-Accurate Fractional- Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital- Modulator-Based Divider Controller”, IEEE journal of solid state circuits, Vol. 49, No. 7, pp. 1595-1605, 2014.
 S.A. Sadatnoori, E. Farshidi and S. Sadughi, “A novel structure of dithered nested digital delta-sigma modulator with low-complexity low-spur for fractional frequency synthesizers”, COMPEL - The international journal for computation and mathematics in electrical and electronic, Vol. 35, No. 1, pp. 157-171, 2016.
 S.A. Sadatnoori, E. Farshidi and S. Sadughi, “A Novel Architecture of Pseudorandom Dithered MASH Digital Delta-Sigma Modulator with Lower Spur ”, Journal of Circuits, Systems and Computers, Vol. 25, No. 7: pp. 1650072-1, 1650072-18, 2016.
 H. Mo and M.P. Kennedy, “Masked Dithering of MASH Digital Delta-Sigma Modulators With Constant Inputs Using Multiple Linear Feedback Shift Registers, IEEE Transactions on Circuits and Systems I: Regular Papers, 64(6) , 1390-1399, (2017).
 Y. Zhang, R. Wunderlich and S. Heinen, “A low-complexity low-spurs digital architecture for wideband PLL applications”, Microelectronics Journal, Vol. 45, pp. 842847, 2014.
 W.J. Lancioni, F.C. Dualibe, P. Petrashin, L. Toledo and L. Vazquez, “Continuous time full-feedforward MASH 2-2 architecture for sigma-delta modulators”, 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), pp. 1-4, 2018.
 Y. Liao, X. Fan and Z. Hua, “Influence of LFSR Dither on the Periods of a MASH Digital Delta-Sigma Modulator”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 66, No. 1, pp. 66-70, 2019.
 Z. Ye. and M.P. Kennedy, “Hardware reduction in digital delta-sigma modulators via error masking—Part I: MASH DDSM”,IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 56, No. 4, pp. 714–726, 2009.
 Z. Ye. and M.P. Kennedy, “Hardware reduction in digital delta-sigma modulators via error masking—Part II: SQDDSM”, IEEE Trans. CircuitsSyst. II, Exp. Briefs, Vol. 56, No. 2, pp. 112–116, 2009.
 Y. Liao , X. Fan and Z. Hua, “Influence of LFSR Dither on the Periods of a MASH Digital Delta–Sigma Modulator”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 66, No. 1, pp. 66-70, 2019.
 L. Le and G. Chen, “Designing and Optimizing of SigmaDelta Modulator Using PSO Algorithm”, IEEE International Conference of Safety Produce Informatization (IICSPI), China, 2019.
 V. Mazzaro and M.P. Kennedy, “Mitigation of Horn Spurs in a MASH-Based Fractional-N CP-PLL”; IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 67, No. 5, pp. 821-825, 2020.
 D. Mai and M.P. Kennedy, “Analysis of Wandering Spur Patterns in a Fractional- N Frequency Synthesizer With a MASH-Based Divider Controller”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 67, No. 3, pp. 729-742, 2020.
 A. Shamsi, “A new Mismatch cancelation for Quadrature Delta-Sigma Modulator”; International Journal of Industrial Electronics Control and Optimization IECO, Vol. 3, No. 2,pp. 196-204, 2020.
 D. Mai, Y. Donnelly, M.P. Kennedy,S. Tulisi, J. Breslin, P. Griffin, M. Connor, S. Brookes, B. Shelly and M. Keaveney, “Wandering Spur Suppression in a 4.9-GHz Fractional-N Frequency Synthesizer”, IEEE Journal of Solid-State Circuits , Vo1. 1, No.1, 2022.
 A.M. Abdul and U.R. Nelakuditi, “A Linearized Charge Pump for Power and Phase Noise Efficient Fractional-N PLL Design”, 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI), 2021.
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